RFXCOM RFXtrx433 Especificações descarregar pdf (Página 51)

Chapter 4. Implementation 44

Figure 4.9.: Diﬀerent data streams recorded with the scanalogic 2 logic analyser. The blue trace

is the reference data received with a RF Link receiver, the other three traces are from

the RFM22B. The time delay between the reference and the deglitched output is

due to the ﬁltering algorithm. It is easy to recognize the impact of the AGC, as it

causes rustling during intermissions or longer breaks. The green trace is the rx-clock

generated by a clock recovery circuit from the data input and ﬁlter parameters. Its

frequency is approximately 38 kHz; however, the irregularities in the picture are due

to the low sampling frequency of logic analyser, they do not exist in reality.

1 ISR ( PORTE_INT2_vect )

2 {

3 static uint8_t st r eam = 0 ; // bit stream of incoming data

4 static uint8_t c ount = 0 ; // number of last ’1’- bits

6 if (PORTE_IN & RFM_GPIO2) {

7 str e am = ( s tre am << 1 ) | 1 ;

8 co un t++;

9 }

10 else {

11 if ( c ou nt < DEGLITCH_MIN_PULSES) {

12 st re am &= ( 0xF F << co un t ) ;

13 }

14 co un t = 0 ;

15 str e am <<= 1 ;

16 }

17 d e te c t_ e d g es ( ) ;

18 }

Listing 4.1: The deglitching algorithm.

The last part in the signal chain is the processing block. It is still the old code that was used in the

WiﬁControl 433 ﬁrmware; however, it was optimized and restructured. It consists of a function

for processing and a timer unit for time measurements as well as recognition of the end of data

packages. The function is called each time an edge occurs in the deglitched output. First, the

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RFXCOM RFXtrx433 Especificações Página 51